hsmp-386x surface mount pin diodes data sheet features ? unique confgurations in surface mount packages C add flexibility C save board space C reduce cost ? switching C low distortion switching C low capacitance ? attenuating C low current attenuating for less power consumption ? matched diodes for consistent performance ? better thermal conductivity for higher power dissipation ? low failure in time (fit) rate [1] ? lead-free note: 1. for more information see the surface mount pin reliability data sheet. description/applications the hsmp-386x series of general purpose pin diodes are designed for two classes of applications. the frst is attenu - ators where current consumption is the most important design consideration. the second application for this series of diodes is in switches where low capacitance is the driving issue for the designer. the hsmp-386x series total capacitance (c t ) and total resistance (r t ) are typical specifcations. for applications that require guaranteed performance, the general purpose hsmp-383x series is recommended. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime. pin connections and package marking, sot-363 notes: 1. package marking provides orientation, identifcation, and date code. 2. see electrical specifcations for appropriate package marking. lux 1 2 3 6 5 4
2 package lead code identifcation, sot-23, sot-143 (top view) package lead code identifcation, sot-323 (top view) common cathode #4 common anode #3 series #2 single #0 common cathode f common anode e series c single b package lead code identifcation, sot-363 (top view) unconnected trio l 12 3 65 4 electrical specifcations t c = 25c, each diode pin general purpose diodes, typical specifcations t a = 25c package minimum typical typical part number marking lead breakdown series resistance total capacitance hsmp- code code confguration voltage v br (v) r s (?) c t (pf) 3860 l0 0 single 50 3.0/1.5* 0.20 3862 l2 2 series 3863 l3 3 common anode 3864 l4 4 common cathode 386b l0 b single 386c l2 c series 386e l3 e common anode 386f l4 f common cathode 386l ll l unconnected trio test conditions v r = v br i f = 10 ma v r = 50 v measure f = 100 mhz f = 1 mhz i r f 10 a i f = 100 ma* absolute maximum ratings [1] t c = +25c symbol parameter unit sot-23 sot-323 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v 50 50 t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 q jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is defned to be the temperature at the package pins where contact is made to the circuit board. esd warning: handling precautions should be taken to avoid static discharge. ring quad d 1 3 2 4 see separate data sheet hsmp-386d
3 hsmp-386x typical parameters at t c = 25c part number total resistance carrier lifetime reverse recovery time total capacitance hsmp- r t (?) t (ns) t rr (ns) c t (pf) 386x 22 500 80 0.20 test conditions i f = 1 ma i f = 50 ma v r = 10 v v r = 50 v f = 100 mhz t r = 250 ma i f = 20 ma f = 1 mhz 90% recovery typical performance, t c = 25c, each diode figure 1. rf capacitance vs. reverse bias. 0.15 0.30 0.25 0.20 0.35 02 6 41 01 2 81 6 14 18 20 total capacitance (pf) reverse voltage (v) 1 ghz 100 mhz 1 mhz 120 11 5 11 0 105 100 95 90 85 11 03 0 i f C forward bias current (ma) figure 3. 2nd harmonic input intercept point vs. forward bias current for switch diodes. input intercept point (dbm) diode mounted as a series switch in a 50 microstrip and t ested at 123 mhz forward current (ma) figure 4. reverse recovery time vs. forward current for various reverse voltages. t rr C reverse recovery time (ns) 10 100 1000 10 20 30 v r = 5 v v r = 10 v v r = 20 v figure 2. typical rf resistance vs. forward bias current. 0.01 100 1000 1 10 resistance (ohms) bias current (ma) 10 100 1 0.1 t a = +85 c t a = +25 c t a = C 55 c 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f C forward current (ma) v f C forward voltage (ma) figure 5. forward current vs. forward voltage. 125 c 25 c C 50 c equivalent circuit model hsmp-386x chip* 0.12 pf 1.5 r j r s c j r j = 12 i 0.9 r t = 1.5 + r j c t = c p + c j ? i = forwar d bias current in ma * see an1124 f or pac kage models
4 typical applications for multiple diode products figure 10. four diode attenuator. see an1048 for details. input rf in/out figure 10. four diode p attenuator . see an1048 for details. fixed bias voltage variable bias figure 6. simple spdt switch, using only positive current. figure 7. high isolation spdt switch, dual bias. figure 8. switch using both positive and negative current. figure 9. very high isolation spdt switch, dual bias. rf common rf 1 bias 1 rf 2 bias 2 rf common rf 1 rf 2 bias rf common rf 2 rf 1 bias rf common bias bias rf 2 rf 1
5 typical applications for multiple diode products (continued) rf in rf out 1 +v 0 2 0 +v on off 4 5 6 1 11 2 2 3 1 1 2 3 4 0 56 b1 b2 b3 2 3 1 11 rf in rf out 2 2 3 45 6 1 0 0 2 +v Cv on off figure 12. hsmp-386l unconnected trio used in a positive voltage, high isolation switch. figure 14. hsmp-386l unconnected trio used in a dual voltage, high isolation switch. figure 13. hsmp-386l used in a sp3t switch. figure 1 1. high isolation spst switch (repeat cells as required). bias figure 11. high isolation spst switch (repeat cells as required).
6 assembly information sot-323 pcb footprint recommended pcb pad layouts for the miniature sot packages are shown in figures 15, 16, 17. these layouts provide ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 0.039 0.079 0.022 dimensions in inches figure 15. recommended pcb pad layout for avagos sc70 3l/sot -323 products. 0.026 0.079 0.018 0.039 dimensions in inches figure 16. recommended pcb pad layout for avagos sc70 6l/sot-363 products. 0.039 1 0.039 1 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 figure 17. recommended pcb pad layout for avagos sot-23 products. ordering information specify part number followed by option. for example: hsmp - 386x - xxx bulk or tape and reel option part number; x = lead code surface mount pin option descriptions -blkg = bulk, 100 pcs. per antistatic bag -tr1g = tape and reel, 3000 devices per 7" reel -tr2g = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement.
7 lead-free refow profle recommendation (ipc/jedec j-std-020c) refow parameter lead-free assembly average ramp-up rate (liquidus temperature (t s(max) to peak) 3c/ second max preheat temperature min (t s(min) ) 150c temperature max (t s(max) ) 200c time (min to max) (t s ) 60-180 seconds ts(max) to tl ramp-up rate 3c/second max time maintained above: temperature (t l ) 217c time (t l ) 60-150 seconds peak temperature (t p ) 260 +0/-5c time within 5 c of actual peak temperature (t p ) 20-40 seconds ramp-down rate 6c/second max time 25 c to peak temperature 8 minutes max note 1: all temperatures refer to topside of the package, measured on the package body surface figure 18. surface mount assembly profle. 2 5 t i m e t e m p e r a t u r e t p t l t p t l t 2 5 c t o p e a k r a m p - u p t s t s m i n r a m p - d o w n p r e h e a t c r i t i c a l z o n e t l t o t p t s m a x smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase refow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot package, will reach solder refow temperatures faster than those with a greater mass. avagos diodes have been qualifed to the time-temper - ature profle shown in figure 18. this profle is represen - tative of an ir refow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evapo - rating solvents from the solder paste. the refow zone briefy elevates the temperature sufciently to produce a refow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. the maximum temperature in the refow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assembly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refow of solder.
8 package dimensions outline 23 (sot-23) package characteristics lead material ........................................... copper (sot-323/363); alloy 42 (sot-23) lead finish ......................................................................... tin 100% (lead-free option) maximum soldering temperature ............................................ 260c for 5 seconds minimum lead strength ........................................................................... 2 pounds pull typical package inductance ...................................................................................... 2 nh typical package capacitance .............................................. 0.08 pf (opposite leads) outline sot-323 (sc-70, 3 lead) outline 363 (sc-70, 6 lead) e b e2 e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 max. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 symbol a a1 b c d e1 e e1 e2 e l e b e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.80 0.00 0.15 0.08 1.80 1.10 1.80 0.26 max. 1.00 0.10 0.40 0.25 2.25 1.40 2.40 0.46 symbol a a1 b c d e1 e e1 e l 1.30 typical 0.65 typical e he d e a1 b a a2 dimensions (mm) min. 1.15 1.80 1.80 0.80 0.80 0.00 0.15 0.08 0.10 max. 1.35 2.25 2.40 1.10 1.00 0.10 0.30 0.25 0.46 symbol e d he a a2 a1 e b c l 0.650 bcs l c
9 user feed direction cover tape carrier tape reel note: "ab" represents package marking code. "c" represents date code. end vie w 8 mm 4 mm top view abc abc abc abc end vie w 8 mm 4 mm top view note: "ab" represents package marking code. "c" represents date code. abc abc abc abc device orientation tape dimensions and product orientation for outline sot-23 for outlines sot-23, -323 for outline sot-363 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0 .05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 - 0.10 0.229 0.013 0.315 + 0.012 - 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline
tape dimensions and product orientation for outlines sot-323, -363 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.0?4 0.004 0.0?4 0.004 0.04? ? 0.004 0.15? 0.004 0.0?? + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.?5 0.10 0.0?1 0.002 0.15? 0.004 0.0?? 0.004 perforation width thickness w t 1 ?.00 0.?0 0.254 0.02 0.?15 0.012 0.0100 0.000? carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 ?.50 0.05 2.00 0.05 0.1?? 0.002 0.0?? 0.002 distance for sot??2? (sc?0?? lead) an ? c ma? for sot???? (sc?0?? lead) 10 c ma? angle width tape thickness c t t 5.4 0.10 0.0?2 0.001 0.205 0.004 0.0025 0.00004 cover tape for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. obsoletes 5989-4028en av02-0293en - october 21, 2013
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